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| cy7c4122kv13/cy7c4142kv13 144-mbit qdr?-iv xp sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-68255 rev. *m revised november 19, 2014 144-mbit qdr?-iv xp sram features 144-mbit density (8 m 18, 4 m 36) total random transaction rate [1] of 2132 mt/s maximum operating frequency of 1066 mhz read latency of 8.0 clock cycles and write latency of 5.0 clock cycles eight-bank architectu re enables one acce ss per bank per cycle two-word burst on all accesses dual independent bidirectional data ports ? double data rate (ddr) data ports ? supports concurrent read/write transactions on both ports single address port used to control both data ports ? ddr address signaling single data rate (sdr) control signaling high-speed transceiver logic (hstl) and stub series termi- nated logic (sstl) compatible signaling (jesd8-16a compliant) ? i/o v ddq = 1.2 v 50 mv or 1.25 v 50 mv pseudo open drain (pod) signaling (jesd8-24 compliant) ? i/o v ddq = 1.1 v 50 mv or 1.2 v 50 mv core voltage ? v dd = 1.3 v 40 mv on-die termination (odt) ? programmable for clock, address/command, and data inputs internal self-calibration of ou tput impedance through zq pin bus inversion to reduce switching noise and power ? programmable on/off for address and data address bus parity error protection training sequence for per-bit deskew on-chip error correction code (ecc) to reduce soft error rate (ser) jtag 1149.1 test access port (jesd8-26 compliant) ? 1.3 v lvcmos signaling available in 361-ball fcbga pb-free package (21 21 mm) configurations cy7c4122kv13 ? 8 m 18 cy7c4142kv13 ? 4 m 36 functional description the qdr-iv xp (xtreme performance) sram is a high-performance memory device optimized to maximize the number of random transactions per second by the use of two independent bidirectional data ports. these ports are equipped with ddr interfaces and designated as port a and port b respectively. accesses to these two data ports are concurrent and independent of each other. access to each port is through a common address bus running at ddr. the control signals are running at sdr and determine if a read or write should be performed. there are three types of differential clocks: (ck, ck#) for address and command clocking (dka, dka#, dkb, dkb#) for data input clocking (qka, qka#, qkb, qkb#) fo r data output clocking addresses for port a are latched on the rising edge of the input clock (ck), and addresses for port b are latched on the falling edge of the input clock (ck). this qdr-iv xp sram is internally partitioned into eight internal banks. each bank can be acce ssed once for every clock cycle, enabling the sram to oper ate at high frequencies. the qdr-iv xp sram device is offered in a two-word burst option and is available in 18 and 36 bus width configurations. for an 18 bus-width configurat ion, there are 22 address bits, and for an 36 bus width configuration, there are 21 address bits respectively. an on-chip ecc circuitry dete cts and corrects all single-bit memory errors including those induced by soft error events, such as cosmic rays and alpha particle s. the resulting ser of these devices is expected to be less than 0.01 fits/mb, a four-order-of-magnitude improvement over previous generation srams. for a complete list of related resources, click here . selection guide description qdr-iv 2132 (mt/s) qdr-iv 1866 (mt/s) unit maximum operating frequency 1066 933 mhz maximum operating current 18 4100 3400 ma 36 4500 4000 note 1. rtr (random transaction rate) is defined as the number of fully random memory accesses (reads or writes) that can be performe d on the memory. rtr is measured in million transactions per second.
cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 2 of 51 logic block diagram ? cy7c4122kv13 cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 3 of 51 logic block diagram ? cy7c4142kv13 cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 4 of 51 contents pin configurations ........................................................... 5 pin definitions .................................................................. 7 functional overview ........................................................ 9 clocking ....................................................................... 9 command cycles ........................................................ 9 read and write data cycles ....................................... 9 banking operation ....................................................... 9 address and data bus inversi on ................................. 9 address parity ........................................................... 10 port enable ............ .............. .............. .............. .......... 10 on-die termination (odt) operation ....................... 10 jtag operation ........................................................ 10 power-up and reset ................................................. 10 operation modes ....................................................... 11 deskew training sequence ...... .............. ........... ....... 12 i/o signaling standards ............................................ 12 initialization ................................................................ 13 configuration registers ............................................. 14 configuration registers description .......................... 15 configuration register definitions ............................. 15 i/otype and port enable bit de finitions ..... ........... .... 17 odt termination bit definitions ................................ 18 drive strength bit definitions .................................... 19 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 20 test access port ....................................................... 20 tap registers ........................................................... 20 tap instruction set ................................................... 20 tap controller state diagram ....................................... 22 tap controller block diagram ...................................... 23 tap electrical characteristics ...................................... 24 tap ac switching characteristics ............................... 24 tap timing diagram ...................................................... 25 identification register definitions ................................ 26 scan register sizes ....................................................... 26 instruction codes ........................................................... 26 boundary scan order .................................................... 27 maximum ratings ........................................................... 30 operating range ............................................................. 30 neutron soft error immunity ......................................... 30 electrical characteristics ............................................... 30 capacitance .................................................................... 32 thermal resistance ........................................................ 32 ac test load and waveform ......................................... 32 switching characteristics .............................................. 33 switching waveforms .................................................... 35 ordering information ...................................................... 42 ordering code definitions ..... .................................... 42 package diagram ............................................................ 43 acronyms ........................................................................ 44 document conventions ................................................. 44 units of measure ....................................................... 44 errata ............................................................................... 45 part numbers affected .............................................. 45 qdr-iv qualification status ...................................... 45 qdr-iv errata summary ....... .................................... 45 document history page ................................................. 50 sales, solutions, and legal information ...................... 51 worldwide sales and design s upport ......... .............. 51 products .................................................................... 51 psoc? solutions ...................................................... 51 cypress developer community ................................. 51 technical support ................. .................................... 51 cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 5 of 51 pin configurations figure 1. 361-ball fcbga pinout cy7c4122kv13 (8 m 18) cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 6 of 51 figure 2. 361-ball fcbga pinout cy7c4142kv13 (4 m 36) pin configurations (continued) cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 7 of 51 pin definitions pin name i/os pin description ck, ck# input clock address/command input clock . ck and ck# are differential clo ck inputs. all control and address input signals are sampled on both the rising and falling edges of ck. the rising edge of ck samples the control and address inputs for port a, while the falling edge of ck samples the control and address inputs for port b. ck# is 180 degrees out of phase with ck. a[x:0] input address inputs . sampled on the rising edge of both ck and ck# clocks du ring active read and write operations. these address inputs are used for read and write operations on both ports. the lower three address pins (a0, a1, and a2) select the ba nk that will be accessed. these address inputs are also known as bank address pins. for (36) data width - address inputs a[20:0] are used and a[24:21] are reserved. for (18) data width - address inputs a[21:0] are used and a[24:22] are reserved. the reserved address inputs are no connects and may be tied high, tied low, or left floating. ap input address parity input . used to provide even parity across the address pins. for (36) data width - ap covers address inputs a[20:0] for (18) data width - ap covers address inputs a[21:0] pe# output address parity error flag . asserted low when address parity e rror is detected. once asserted, pe# will remain low until cleared by a configuration register command. ainv input address inversion pin for address and address parity inputs . for (36) data width - ainv covers address in puts a[20:0] and the add ress parity input (ap). for (18) data width - ainv covers address in puts a[21:0] and the add ress parity input (ap). dka[1:0], dka#[1:0], dkb[1:0], dkb#[1:0] input data input clock . dka[0] / dka#[0] controls the dqa[17:0] inputs for 36 configuration and dqa[8:0] inputs for 18 configuration respectively dka[1] / dka#[1] controls the dqa[35:18] inputs fo r 36 configuration and dqa[17:9] inputs for 18 configuration respectively dkb[0] / dkb#[0] controls the dqb[17:0] inputs for 36 configuration and dqb[8:0] inputs for 18 configuration respectively dkb[1] / dkb#[1] controls the dqb[35:18] inputs fo r 36 configuration and dqb[17:9] inputs for 18 configuration respectively qka[1:0], qka#[1:0], qkb[1:0], qkb#[1:0] output data output clock . qka[0] / qka#[0] controls the dqa[17:0] outputs fo r 36 configuration and dq a[8:0] outputs for 18 configuration respectively qka[1] / qka#[1] controls the dq a[35:18] outputs for 36 configur ation and dqa[17:9] outputs for 18 configuration respectively qkb[0] / qkb#[0] controls the dqb[17:0] outputs fo r 36 configuration and dq b[8:0] outputs for 18 configuration respectively qkb[1] / qkb#[1] controls the dq b[35:18] outputs for 36 configur ation and dqb[17:9] outputs for 18 configuration respectively dqa[x:0], dqb[x:0] input/output data input/output .bidirectional data bus. for (36) data width ? dqa [35:0] ; dqb [35:0] for (18) data width ? dqa [17:0] ; dqb [17:0] dinva[1:0], dinvb[1:0] input/output data inversion pin for dq data bus . dinva[0] covers dqa[17:0] for 3 6 configuration and dqa[8:0] fo r 18 configuration respectively dinva[1] covers dqa[35:18] for 36 configuration and dqa[17:9] fo r 18 configuration respectively dinvb[0] covers dqb[17:0] for 3 6 configuration and dqb[8:0] fo r 18 configuration respectively dinvb[1] covers dqb[35: 18] for 36 configuration and dqb[17:9] for 18 configuration respectively lda#, ldb# input synchronous load input . lda# is sampled on the rising edge of the ck clock, while ldb# is sampled on the falling edge of ck clock. lda# enables commands for data port a and ldb# enables commands for data port b. ldx# enables the commands when ldx# is low and disables the commands when ldx# is high. when the command is disabled, new commands are ignored, but internal operations continue. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 8 of 51 rwa#, rwb# input synchronous read/write input . rwa# input is sampled on the rising edge of the ck clock, while rwb# is sampled on the falling edge of the ck clock. the rwa# input is used in conjunction with the lda# input to select a read or write operation. si milarly, the rwb# input is used in conjunction with the ldb# input to select a read or write operation. qvlda [1:0], qvldb [1:0] output output data valid indicator . the qvld pin indicates valid out put data. qvld is edge-aligned with qkx and qkx#. zq/zt input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. cfg# input configuration bit . this pin is used to configure different mode registers. rst# input active low asynchronous rst . this pin is active when rst# is low and inactive when rst# is high. the rst# pin has an internal pull-down resistor. lbk0#, lbk1# input loopback mode for control and address/command/clock deskewing . tms input test mode select input pin for jtag . this pin may be left unconnected if the jtag function is not used in the circuit. tdi input test data input pin for jtag . this pin may be left unconnected if the jtag function is not used in the circuit. tck input test clock input pin for jtag . this pin must be tied to vss if th e jtag function is not used in the circuit. tdo output test data output pin for jtag . this pin may be left unconnected if the jtag function is not used in the circuit. trst# input test reset input pin for jtag . this pin must be tied to vdd if the jtag function is not used in the system. trst# input is applicable only in jtag mode. dnu n/a do not use . do not use pins. vref reference reference voltage input . static input used to set the reference level for inputs, outputs, and ac measurement points. vdd power power supply inputs to the core of the device . vddq power power supply inputs for the outputs of the device . vss ground ground for the device . pin definitions (continued) pin name i/os pin description cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 9 of 51 functional overview the qdr-iv xp sram is a two-word burst synchronous sram equipped with dual independent bidirectional data ports. the following sections describe the device operation. clocking there are three groups of clock signals: ck/ck#, dkx/dkx#, and qkx/qkx#, where x can be a or b, referring to the respective ports. the ck/ck# clock is associated with the address and control pins: a[24:0], lda#, ldb# , rwa#, rwb#. the ck/ck# transitions are centered with resp ect to the address and control signal transitions. the dkx/dkx# clocks are associated with write data. the dkx/dkx# clocks are used as source-centered clocks for the ddr dqx and dinvx pins, when acting as inputs for the write data. the qkx/qkx# clocks are associ ated with read data. the qkx/qkx# clocks are used as source-synchronous clocks for the double data rate dqx a nd dinvx pins, when acting as outputs for the read data. command cycles the qdr-iv xp sram read and write commands are driven by the control inputs (lda#, ldb#, rwa#, and rwb#) and the address bus. the port a control inputs (lda# and rwa#) are sampled at the rising edge of the input clock. the port b control inputs (ldb# and rwb#) are sampled at the falling edge of the input clock. for port a: when lda# = 0 and rwa# = 1, a read operation is initiated. when lda# = 0 and rwa# = 0, a write operation is initiated. the address is sampled on the rising edge of the input clock. for port b: when ldb# = 0 and rwb# = 1, a read operation is initiated. when ldb# = 0 and rwb# = 0, a write operation is initiated. the address is sampled on the falling edge of the input clock. read and write data cycles read data is supplied to the dqa pins exactly eight clock cycles from the rising edge of the ck signal corresponding to the cycle where the read command was initiated. qvlda is asserted one-half clock cycle prior to the fi rst data word driven on the bus. it is deasserted one-half cycle prio r to the last data word driven on the bus. data outputs are tristated in the clock following the last data word. read data is supplied to the dqb pins exactly eight clock cycles from the falling edge of the ck signal corresponding to the cycle that the read command was initiated. qvldb is asserted one-half clock cycle prior to the fi rst data word driven on the bus. it is deasserted one-half cycle prio r to the last data word driven on the bus. data outputs are tristated in the clock following the last data word. write data is supplied to the dq a pins exactly five clock cycles from the rising edge of the ck signal corresponding to the cycle that the write command was initiated. write data is supplied to the dq b pins exactly five clock cycles from the falling edge of the ck signal corresponding to the cycle that the write command was initiated. banking operation the qdr-iv xp sram is designed with eight internal banks. the lower three address pins (a0, a1, and a2) select the bank that will be accessed. these address inputs are also known as bank address pins. bank access rules 1. on the rising edge of the input clock, any bank address may be accessed. this is the address associated with port a. 2. on the falling edge of the input clock, any other bank address may be accessed. this is the address associated with port b. 3. if port a did not issue a command on the rising edge of the input clock, then port b may access any bank address on the falling edge of the input clock. 4. from the rising edge of the input clock cycle to the next rising edge of the input clock, there is no address restriction . port a may access any bank at any time. to clarify, the banking restriction only applies in a single clock cycle. since the port a address is sampled on the rising edge of the input clock, there are no restrictions with port a access. because the port b address is sampled on the falling edge of the input clock, port b has the restriction that it must use a different bank than port a. banking violations 1. accesses for port a cannot cause a banking violation, only accesses to port b can. 2. if port b tries to access the same bank as port a, then the port b access to the memory array is ignored . the port a access will still occur normally. 3. if the requested cycle on port b was a write, then there will be no external indication that a banking violation occurred. 4. if the requested cycle on port b was a read, then there will be no qvldb signal generated. outputs will remain tristated. address and data bus inversion to reduce simultaneous switching noise and i/o current, qdr-iv xp sram provides the ability to invert all address and data pins. the ainv pin indicates whether the address bus, a[24:0], and the address parity bit, ap, is inverted. the address bus and parity bit are considered one group. the function of the ainv is controlled by the memory controller. however, the following rules should be used in the system design: for a 36 configuration part, 21 address pins plus 1 parity bit are used for 22 signals in the address group.if the number of 0?s in the address group is > 11, ainv is set to 1 by the controller. as a result, no more than 11 pins may switch in the same direction during each bit time. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 10 of 51 for a 18 data width part, 22 address pins plus 1 parity bit are used for 23 signals in the address group. if the number of 0?s in the address group is > 12, ainv is set to 1 by the controller. as a result, no more than 12 pins may switch in the same direction during each bit time. the dinva and dinvb pins indicate whether the corresponding dqa and dqb pins are inverted. for a 36 data width part, the data bus for each port is split into groups of 18 pins. each 18-pin data group is guaranteed to be driving less than or equal to 10 pins low on any given cycle.if the number of 0?s in the data group is > 10, dinv is set to 1. as a result, no more than 10 pins ma y switch in the same direction during each bit time. for a 18 data width part, the data bus for each port is split into groups of 9 pins. each 9-pin data group is guaranteed to be driving less than or equal to five pins low on any given cycle. if the number of 0?s in the data group is > 5, dinv is set to 1. as a result, no more than five pins may switch in the same direction during each bit time. ainv, dinva[1:0], dinvb[ 1:0] are all active high. when set to 1, the corresponding bus is inverted . if the data inve rsion feature is programmed to be off, then t he dinva/dinvb output bits will always be driven to 0. these functions are programmab le through the configuration registers and can be enabled or disabled for the address bus and the data bus independently. during configuration register read and write cycles, the address inversion input is ignored and the data inversion output is always driven to 0 when the register read data is driven on the data bus. specifically, the register read data is driven on dqa[7:0] and the dinva[0] bit is driven to 0. all other dqa/dqb data bits and dinva/dinvb bits are tristated. in addition, the address parity input (ap) is ignored. address parity the qdr-iv xp sram provides an address parity feature to provide integrity on the address bus. two pins are provided to support this function: ap and pe#. the ap pin is used to provide an even parity across the address pins. the value of ap is set so that the total number of 1?s (including the ap bit) is even. the ap pin is a ddr input. internally, when an address parity error is detected, the access to the memory array is ignored if it was a write cycle. a read access continues normally even if an address parity error is detected. externally, the pe# pin is used to indicate that an address parity error has occurred. this pin is active low and is set to 0 within rl cycles after the address parity error is detected. it remains asserted until the error is cl eared through the configuration registers. the address parity function is optional and can be enabled or disabled in the configuration registers. during configuration register read and write cycles, the address parity input is ignored. parity is not checked during these cycles. note the memory controller should generate address parity based on the address bus first. address inversion is done later on the address bus and address parity bit. port enable the qdr-iv xp sram has two independent bidirectional data ports. however, some system designers may either choose to use only one port, or use one port as read-only and one port as write-only. if a port is used in a unidirectional mode, disable the data clocks (dkx/dkx# or qkx/qkx#) to reduce emi effects in the system. in addition, disable the corresponding control input (rwx#). port b may be programmed to be entirely disabled. if port b is not used, then the following must happen: the data clocks (dkb/dkb# and qkb/qkb#) and the control inputs (ldb# and rwb#) must be disabled. all data bus signals must be tri-stated. this includes dqb, dinvb, and qvldb. all input signals related to port b can be left floating or tied to either 1 or 0 without any adverse effects on the port a operation. when port b is not used, all out put signals related to port b are inactive. a configuration register option is provided to specify if one of the ports is not used or is opera ting in a unidirectional mode. on-die termination (odt) operation when enabled, the odt circuits for the chip will be enabled during all nop and write cycles. the odt is temporarily disabled only during read cycles because the read data is driven out. specifically, odt is disabled one-half clock cycle before the first beat of the read data is driven on the data bus and remains disabled during the entire read oper ation. odt is enabled again one-half clock cycle after the last beat of read data is driven on the data bus. jtag operation the jtag interface uses five signals: trst#, tck, tms, tdi, and tdo. for normal jtag operation, the use of trst# is not optional for this device. while in the jtag mode, the following conditions are true: odt for all pins is disabled. if the jtag function is not us ed in the system, then the trst# pin must be tied to vdd and the tck input must be driven low or tied to vss. tms, tdi, and tdo may be left floating. power-up and reset the qdr-iv xp sram has specific power-up and reset requirements to guarantee reliable operation. power-up sequence apply v dd before v ddq . apply v ddq before v ref or at the same time as v ref . cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 11 of 51 reset sequence refer to the reset timing diagram ( figure 16 on page 41 ). 1. as the power comes up, all inputs may be in an undefined state, except rst# and trst #, which must be low during t pwr . 2. the first signal that should be driven to the device is the input clock (ck/ck#), which may be unstable for the duration of t pwr . 3. after the input clock has stab ilized, all the control inputs should be driven to a valid value as follows: a. rst# = 0 b. cfg# = 1 c. lbk0# = 1 d. lbk1# = 1 e. lda# = 1 f. ldb# = 1 4. reset should remain asserted, while all other control inputs deasserted, for a minimum time of 200 s (t rss ). 5. at the rising edge of reset, the address bits a[13:0] are sampled to load in the odt values and port enable values. after reset, internal operations in the de vice may start. this may include operations, such as pll initialization and resetting internal registers. 6. however, all external control signals must remain deasserted for a minimum time of 400000 clocks (t rsh ). during this time all other signals (data and address busses) should be driven to a valid level. all inputs to the device should be driven to a valid level. 7. after this, the device is in normal operating mode and ready to respond to control inputs. typically, after a reset sequence, the system starts to perform a training sequence involving the steps outlined in the following section. however, rst# may be asserted at any time by the system and the system may wish to initiate no rmal read/write op erations after a reset sequence, without going through another training sequence. the chip should be able to accept normal read/write operations immediately following t rsh after the deassertion of rst#. pll reset operation the configuration registers contain a bit to reset the pll. operating the qdr-iv xp sram device without the pll enabled is not supported?timing char acteristics are not guaranteed when the pll is disabled. however, this bit is intended to allow the system to reset the pll locking circuitry. resetting the pll is accomplished by first programming the pll reset bit to 1 to disable the pll, and then programming the bit to 0 to enable the pll. after these steps, the pll will relock to the input clock. a wait time of tpll is required. operation modes the qdr-iv xp sram has three unique modes of operation: 1. configuration 2. loopback 3. memory access these modes are defined by t he level of the control signals cfg#, lbk0#, lbk1#, lda#, ldb#. it is intended that these operati ons are mutually exclusive. in other words, one operation mode cannot be performed simultaneously with another operation mode. there is no priority given for inadvertently asserting the control signals at the wrong time. the internal chip behavior is not defined for improper control sign al assertion. the system must strictly adhere to proper mode transitions, as defined in the following sections, for proper device operation. configuration a configuration operation mode is entered when the cfg# signal is asserted. memory access or loopback operations should not be performed for a minimum of 32 clocks prior to entering this mode. while in this mode, the control signals ldb#, lbk0#, and lbk1# must not be asserted. however, lda# is used to perform the actual register read and write operations. memory access or loopback operations should not be performed for a minimum of 32 cl ocks after exiting this mode. loopback a loopback operation mode is entered when the lbk0# and/or lbk1# signals are asserted. memory access or configuration operations should not be performed for a minimum of 32 clocks prior to entering this mode. just after entering this mode, an additional 32 clocks are required before the part is ready to accept toggling valid inputs for training. while in this mode, lda# and ldb# may be toggled for training. memory access or configurat ion operations should not be performed for a minimum of 32 cl ocks after exiting this mode. data inversion is not used during the loopback mode. even if the configuration register has this feature enabled, it is tempo- rarily ignored during the loopback mode. memory access if the control signals cfg#, lbk0#, and lbk1# are not asserted, then the device is in the memo ry access mode. this mode is the normal operating mode of the device. while in this mode, a memory access cycle is performed when the lda# and/or ldb# signals are asserted. the control signals cfg#, lbk0#, and lbk1# must not be asserted when performing a memory access cycle. a memory access should not be performed for a minimum of 32 clocks prior to leaving this mode. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 12 of 51 deskew training sequence the qdr-iv xp sram provides support that allows a memory controller to deskew signals for a high-speed operation. the memory controller provides the deskew function if deskew is desired. during the deskew operation, the qdr-iv xp sram operates in the loopback mode. refer to the loopback timing diagram ( figure 15 on page 40 ). deskew is achieved in three steps: 1. control/address deskew 2. read data deskew 3. write data deskew control/address deskew assert lbk0# to 0 and/or lbk1# to 0. the following 39 signals are looped back: dka0, dka0#, dka1, dka1# dkb0, dkb0#, dkb1, dkb1# lda#, rwa#, ldb#, rwb# a[24:0], ainv, ap the clock inputs dka0, dka0#, dka1#, dkb0, dkb0#, dkb1, and dkb1# are free-running clock inputs and should be continuously running during the training sequence. in addition, a wait time of tpll is needed. refer to table 1 on page 14 for the loopback signal mapping. for each pin that is looped back, the input pin is sampled on both the rising and falling edges using the input clock (ck/ck#). the value output on the rising edge of the output clock (qka/qka#) will be the value that was sampled on the rising edge of the input clock. the value output on the falling edge of the output clock (qka/qka#) will be the inverted value that was sampled on the falling edge of the input clock. the delay from the input pins to the dqa outputs is t lbl , which is 16 clocks. read data deskew at this time, the address, cont rol, and data input clocks are already deskewed. read data deskew requires a training pattern to be written into the memory using data held at constant values. complex data patterns, such as the following, may be written into the memory using the non-deskewed dqa and/or dqb signals and the write training enable bit. write training enable set to 1: during write data cycles: the first data beat (first data burst) is sampled from the data bus. the second data beat (second data burst) is the inverted sample from the same data bus. write training enable set to 0: during write data cycles: both first and second data beats are sampled from the data bus, which is the normal operation. the write training enable bit has no effect on the read data cycles. after the data pattern is written into the memory, standard read commands permit the system to deskew with respect to the qk/qk# data output clocks the following signals: dqa, dinva, qvlda, dqb, dinvb, qvldb write data deskew write data deskew is performed using write commands to the memory followed by read commands. the deskewed read data path is used to determine whether or not the write data was received correctly by the device. this permits the system to deske w with respect to the dk/dk# input data clocks the following signals: dqa, dinva, dqb, dinvb i/o signaling standards several i/o signaling standards are supported by the qdr-iv, which are programmable by the user. they are: 1.2 v and 1.25 v hstl/sstl 1.1 v and 1.2 v pod the i/o signaling standard is programmed on the rising edge of reset by sampling the address bus inputs. once programmed, the value cannot be changed. on ly the rising edge of another reset can change the value. all address, control, and data i/o signals ? with the exception of six pins (listed as lvcmos in the lvcmos signaling section) ? will program to comply with hstl/sstl or pod. hstl/sstl signaling hstl/sstl is supported at the v ddq voltages of 1.2 v and 1.25 v nominal. the odt termination values can be set to: 40, 60, or 120 ohms with a 220-ohm reference resistor 50 or 100 ohms with a 180-ohm reference resistor. the drive strength can be programmed to: 40 or 60 ohms with a 220- ohm reference resistor 50 ohms with a 180-ohm reference resistor a reference resistor of 180 ohms or 220 ohms is supported with hstl/sstl signaling. pod signaling pod is supported at v ddq voltages of 1.1 v and 1.2 v nominal. the odt termination values can be set to: 50 or 100 ohms with a 180-ohm reference resistor 60 or 120 ohms with a 220-ohm reference resistor the drive strength can be programmed to: 50 ohms with a 180-ohm reference resistor 40 or 60 ohms with a 220- ohm reference resistor a reference resistor of 180 ohms or 220 ohms is supported with pod signaling. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 13 of 51 lvcmos signaling six i/o signals are permanently set to use lvcmos signaling at a voltage of 1.3-v nominal. these signals are referenced to the core voltage supply, v dd . they are: rst#, trst#, tck, tms, tdi, and tdo all the five jtag signals as well as the main reset input are 1.3-v lvcmos. in addition, odt is disabled at all times on these lvcmos signals. initialization the qdr-iv xp sram must be initialized before it can operate in the normal functional mode. in itialization uses four special pins: rst# pin to reset the device cfg# pin to program th e configuration registers lbk0# and lbk1# pins for the loopback function the following flowchart illustrates the initialization procedure: figure 3. flowchart illustrating initialization procedure power on apply power to the chip as described in the power-up sequence in power-up sequence . reset chip apply reset to the qdr-iv xp sram as described in reset sequence . configure the impedance assert config (cfg# = 0) and program the impedance control register. wait for the pll to lock since the input impedance is upda ted, allow the pll time (t pll ) to lock to the input clock. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 14 of 51 configure training options at this time, the address and data inversion options need to be programmed. in addition, the write training function needs to be enabled. assert config (cfg# = 0) and program: write training (turn on) address inversion enable data inversion enable control/address deskew control and address deskew can now be performed by the memory controller. read data deskew after control and address deskew, the read data path is deskewed as previously described in deskew training sequence . write data deskew write data path is deskewed following the read data path deskew. configure runtime options after the training is complete, di sable the write training function. finally, enable the address parity option at this time. assert config (cfg# = 0) and program: write training (turn off) parity enable normal operation if the system detects a need to deskew again, the process must start again from the configure training options step.the following table defines the loopback mapping: configuration registers the qdr-iv xp sram contains internal registers that are programmed by the system using a special configuration cycle. these registers are used to enable and control several options, as described this section. all r egisters are 8-bits wide. the write operation is performed using only the address pins to define the register address and register write data. for a read operation, the register read data is provided on the data port a output pins. refer to figure 14 on page 39 for programming details. during the rising edge of rst# , the address pins a[13:0] are sampled. the value sampled beco mes the reset value of certain bits in the registers defined in table 2 on page 15 . this is used to set termination, impedance, and port configuration values immediately upon reset. these values can be overwritten later through a register write operation. when a parity error occurs, the complete address of the first error is recorded in registers 4, 5, 6, and 7 along with the port a/b error bit. the port a/b error bit will indicate from which port the address parity error came ? 0 for port a and 1 for port b. this information will remain latched until cleared by writing a 1 to the address parity error clear bit in register 3. two counters are used to indicate if multiple address parity errors occurred. the port a error count is a running count of the number of parity errors on port a addresses, and similarly the port b error count is a running count of the numb er of parity errors on port b addresses. they will each independently count to a maximum value of 3 and then stop counting. these counters are free-running and they are both reset by writing a 1 to the address parity error clear bit in register 3. table 1. loopback signal mapping input pin lbk0# = 0 lbk1# = 0 input pin lbk0# = 0 lbk1# = 1 input pin lbk0# = 1 lbk1# = 0 output pin a0 a13 dka0 dqa0 a1 a14 dka0# dqa1 a2 a15 dka1 dqa2 a3 a16 dka1# dqa3 a4 a17 lda# dqa4 a5 a18 rwa# dqa5 a6 a19 dkb0 dqa6 a7 a20 dkb0# dqa7 a8 a21 dkb1 dqa8 a9 a22 dkb1# dqa9 a10 a23 ldb# dqa10 a11 a24 rwb# dqa11 a12 ainv ap dqa12 cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 15 of 51 configuration registers description configuration register definitions table 2. configuration register table register address description 0 termination control register 1 impedance control register 2 option control register 3 function control register 4 address parity status register 0 5 address parity status register 1 6 address parity status register 2 7 address parity status register 3 table 3. address 0: termination control register (read/write) function odt global enable odt/zq auto update address / command input group iu[2] address / command input group iu[1] address / command input group iu[0] clock input group ku[2] clock input group ku[1] clock input group ku[0] bit location 7 6 5 4 3 2 1 0 reset value a7 a6 a5 a4 a3 a2 a1 a0 note: odt/zq auto update needs to be turned on if odt/zq configuration is changed table 4. address 1: impedance control register (read/write) function pull-down group pd[1] pull-down group pd[0] pull-up group pu[1] pull-up group pu[0] unused data input group qu[2] data input group qu[1] data input group qu[0] bit location 76543210 reset value 10100a10a9a8 table 5. address 2: option control register (read/write bits 7-3) (read-only bits 2-0) [2] function write train enable data inv enable address inv enable address parity enable pll reset i/o type port enable[1] port enable[0] bit location 76543210 reset value 00000a13a12a11 table 6. address 3: function control register (write only) function unused unused unused unused unused unused unused address parity error clear bit location 76543210 reset value 00000000 note 2. the bits 2-0 are read only and can be changed only on the rising edge of reset cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 16 of 51 table 7. address 4: address parity status register 0 (read only) function port b error count (1:0) port a error count (1:0) port a/b error ainv bit unused unused bit location 7:6 5:4 3 2 1 0 reset value 00 00 0 0 0 0 table 8. address 5: address parity status register 1 (read only) function address (23:16) bit location 7:0 reset value 00000000 note: unused address locations will be read as 0 table 9. address 6: address parity status register 2 (read only) function address (15:8) bit location 7:0 reset value 00000000 table 10. address 7: address parity status register 3 (read only) function address (7:0) bit location 7:0 reset value 00000000 cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 17 of 51 i/otype and port enable bit definitions table 11. i/o type bit definition specified in address 2: option control register i/o type function 0 hstl / sstl 1pod table 12. port enable bit de finition specified in address 2: option control register port enable [1:0] function port b mode port a mode port b clocks and controls port a clocks and controls 0 0 fixed port mode write only read only dkb - on qkb - off ldb# - on rwb# - off dka - off qka - on lda# - on rwa# - off 01 only port a enable disabled enabled dkb - off qkb - off ldb# - off rwb# - off dka - on qka - on lda# - on rwa# - on 1 0 not supported disabled disabled dkb - off qkb - off ldb# - off rwb# - off dka - off qka - off lda# - off rwa# - off 11 both ports enabled enabled enabled dkb - on qkb - on ldb# - on rwb# - on dka - on qka - on lda# - on rwa# - on cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 18 of 51 odt termination bit definitions table 13. clock input group bit definition spec ified in address 0: termination control register odt global enable ku[2:0] divisor value termination value hstl/sstl mode termination value pod mode zt 180 ohm zt 220 ohm zt 180 ohm zt 220 ohm 0xxx? off off off off 1000? off off off off 1 0 0 1 8.33% not supported not supported not supported not supported 1 0 1 0 12.50% not supported not supported not supported not supported 1 0 1 1 16.67% not supported 40 ohm not supported not supported 110025% 50 ohm 60 ohm 50 ohm 60 ohm 110150% 100 ohm 120 ohm 100 ohm 120 ohm 1110? not supported not supported not supported not supported 1111? not supported not supported not supported not supported note: termination values are accurate to +/- 15% zq tolerance is 1% table 14. address/command input group bit definition specified in address 0: termination control register odt global enable iu[2:0] divisor value termination value hstl/ sstl mode termination value pod mode zt 180 ohm zt 220 ohm zt 180 ohm zt 220 ohm 0xxx? off off off off 1000? off off off off 1 0 0 1 8.33% not supported not supported not supported not supported 1 0 1 0 12.50% not supported not supported not supported not supported 1 0 1 1 16.67% not supported 40 ohm not supported not supported 110025% 50 ohm 60 ohm 50 ohm 60 ohm 110150% 100 ohm 120 ohm 100 ohm 120 ohm 1110? not supported not supported not supported not supported 1111? not supported not supported not supported not supported note: termination values are accurate to +/- 15% zq tolerance is 1% table 15. data input group bit definition specified in address 1: impedance control register odt global enable qu[2:0] divisor value termination value hstl/ sstl mode termination value pod mode zt 180 ohm zt 220 ohm zt 180 ohm zt 220 ohm 0xxx? off off off off 1000? off off off off 1 0 0 1 8.33% not supported not supported not supported not supported 1 0 1 0 12.50% not supported not supported not supported not supported 1 0 1 1 16.67% not supported 40 ohm not supported not supported 110025% 50 ohm 60 ohm 50 ohm 60 ohm 110150% 100 ohm 120 ohm 100 ohm 120 ohm 1110? not supported not supported not supported not supported 1111? not supported not supported not supported not supported note: termination values are accurate to +/- 15% zq tolerance is 1% cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 19 of 51 drive strength bit definitions table 16. pull-up driver bit definition speci fied in address 1: impedance control register pu[1:0] divisor value impedance value hstl/ sstl mode impedance value pod mode zt 180 ohm zt 220 ohm zt 180 ohm zt 220 ohm 0 0 14.17% not supported not suppor ted not supported not supported 0 1 16.67% not supported 40 ohm not supported 40 ohm 1 0 25% 50 ohm 60 ohm 50 ohm 60 ohm 1 1 ? not supported not supported not supported not supported note: termination values are accurate to +/- 15% zq tolerance is 1% table 17. pull-down driver bit definition specified in address 1: impedance control register pd[1:0] divisor value impedance value hstl/ sstl mode impedance value pod mode zt 180 ohm zt 220 ohm zt 180 ohm zt 220 ohm 0 0 14.17% not supported not suppor ted not supported not supported 0 1 16.67% not supported 40 ohm not supported 40 ohm 1 0 25% 50 ohm 60 ohm 50 ohm 60 ohm 1 1 ? not supported not supported not supported not supported note: termination values are accurate to +/- 15% zq tolerance is 1% cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 20 of 51 ieee 1149.1 serial boundary scan (jtag) qdr-iv xp srams incorporate a serial boundary scan test access port (tap) in the fcbg a package. this part is fully compliant with ieee standard #11 49.1-2001. in the jtag mode, the odt feature for all pins is disabled. if the jtag function is not used in the circuit, then tck inputs must be driven low or tied to vss. trst#, tms, tdi, and tdo may be left floating. an internal pull-up resistor is implemented on the trst#, tms, and tdi i nputs to ensure that these inputs are high during t pwr . test access port test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see tap controller state diagram on page 22 . tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is active, depending upon the current state of the tap state machine (see instruction codes on page 26 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. test reset (trst#) the trst# input pin is used to reset the tap controller. alternatively, a reset may be performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and can be performed while the sram is ope rating. at power-up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo pins to scan the data in and out of the sram te st circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins, as shown in tap controller block diagram on page 23 . upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is pl aced in a rst state, as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this enables shifting of data through the sram with minimal delay. the bypass register is set low (vss) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload, and sa mple z instructions can be used to capture the contents of the input and output ring. boundary scan order on page 27 shows the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in identification register definitions on page 26 . tap instruction set eight different instructions ar e possible with the three-bit instruction register. all co mbinations are listed in instruction codes on page 26 . three of these instru ctions are listed as reserved and must not be used. the other five instructions are described in this section in detail. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction after it is shift ed in, the tap controller must be moved into the update-ir state. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 21 of 51 idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction register. it also places the instruction register between the tdi and tdo pins and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register at power-up or whenever the tap controller is supplied a test-logic-rst state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high z state until the next command is supplied during the update ir state. both port a and port b are enabled once this command has been executed. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the input and output pins is captured in the boundary scan register. remember that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that an input or output undergoes a transition during the capture-dr state. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap cont roller?s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a de sign to stop (or slow) the clock during a sample/preload instructi on. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when requir ed, that is, while the data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction drives the preloaded data out through the system output pins. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift-dr controller stat e. both port a and port b are enabled after this command is executed. extest output bus tristate ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tristate mode. the boundary scan register has output enable control bits located at bit #49 and bit #50. bit# 49 enables the output pins for dqb and bit#50 enables dqa and pe# pins. when these scan cells, called the ?extest output bus tristate,? are latched into the preload register during the update-dr state in the tap controller, they directly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bi t places the output bus into a high z condition. these bits can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the shift-dr state. during update-dr, the value loaded into that shift-register cell latc hes into the preload register. when the extest instruction is entered, th ese bits directly controls the output q-bus pins. note that these bits are pre-set low to disable the output when the device is powered up, and also when the tap controller is in the test-logic-rst state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 22 of 51 tap controller state diagram figure 4. tap controller state diagram [3] test-logic rst test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir note 3. the 0/1 next to each state represents the value at tms at the rising edge of tck. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 23 of 51 tap controller block diagram figure 5. tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 135 0 1 2 instruction register bypass register selection circuitry selection circuitry tdi tdo tck tms tap controller trst# cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 24 of 51 tap electrical characteristics over the operating range parameter description test conditions min max unit v oh lvcmos high-level output voltage i oh = 100 ? a v dd 0.8 ? v v ol lvcmos low-level output voltage i ol = 100 a ? v dd 0.2 v v ih lvcmos high-level input voltage (dc) v dd 0.7 v dd + 0.2 v v il lvcmos low-level input voltage (dc) ?0.2 v dd 0.3 v i x lvcmos input leakage current ? 10 ? a i oz lvcmos output leakage current ? 10 ? a tap ac switchi ng characteristics over the operating range parameter description min max unit t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high 20 ? ns t tl tck clock low 20 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns note: t cs and t ch refer to setup and hold time requirements of latching data from the boundary scan register. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 25 of 51 tap timing diagram figure 6. tap timing diagram cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 26 of 51 identification regi ster definitions instruction field value description cy7c4122kv13 cy7c4142kv13 revision number (31:29) 000 000 version number. cypress device id (28:12) 11011010101010011 11011010101100011 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 136 instruction codes instruction code description extest 000 captures the input and output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input and output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input and output contents. places the b oundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 27 of 51 boundary scan order bit bump cy7c4142kv13 cy7c4122kv13 36 device 18 device 012adqa<26>dqa<17> 113bdqa<19>dqa<10> 214adqa<25>dqa<16> 315bdqa<35>nc 416adqa<23>dqa<14> 518bdqa<31>nc 6 17c qvlda<1> qvlda<1> 7 16c qka<1> qka<1> 8 14c dqa<20> dqa<11> 912cdqa<18>dqa<9> 10 12d dinva<1> dinva<1> 11 13d dqa<22> dqa<13> 12 15d dqa<21> dqa<12> 13 17d qka#<1> qka#<1> 14 18e dqa<32> nc 15 15f dqa<24> dqa<15> 16 16f dka<1> dka<1> 17 17f dka#<1> dka#<1> 18 18g dqa<33> nc 19 16g dqa<34> nc 20 17h dqa<27> nc 21 15h dqa<28> nc 22 16j dqa<30> nc 23 18j dqa<29> nc 24 18k rst# rst# 25 18l dqb<29> nc 26 16l dqb<30> nc 27 15m dqb<28> nc 28 17m dqb<27> nc 29 18n dqb<33> nc 30 16n dqb<34> nc 31 15p dqb<24> dqb<15> 32 16p dkb<1> dkb<1> 33 17p dkb#<1> dkb#<1> 34 18r dqb<32> nc 35 17t qkb#<1> qkb#<1> 36 15t dqb<21> dqb<12> 37 13t dqb<22> dqb<13> 38 12t dinvb<1> dinvb<1> 39 12u dqb<18> dqb<9> 40 14u dqb<20> dqb<11> 41 16u qkb<1> qkb<1> 42 17u qvldb<1> qvldb<1> 43 18v dqb<31> nc 44 15v dqb<35> nc 45 13v dqb<19> dqb<10> 46 12w dqb<26> dqb<17> cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 28 of 51 47 14w dqb<25> dqb<16> 48 16w dqb<23> dqb<14> 49 internal_dqb internal_dqb 50 internal_dqa internal_dqa 51 10v pe# pe# 52 8p a<15> a<15> 53 7n a<9> a<9> 54 9n nc/1152m nc/576m 55 10p ap ap 56 10n a<2> a<2> 57 11n nc/2304m nc/1152m 58 12p a<16> a<16> 59 13n a<10> a<10> 60 13l a<8> a<8> 61 12m a<12> a<12> 62 11l a<18> a<18> 63 10l rwb# rwb# 64 10m ainv ainv 65 9l a<17> a<17> 66 8m a<11> a<11> 67 7l a<7> a<7> 68 7j a<5> a<5> 69 9j a<19> a<19> 70 10k ck# ck# 71 10j ck ck 72 11j a<20> a<20> 73 13j a<6> a<6> 74 12h ldb# ldb# 75 10h rwa# rwa# 76 8h lda# lda# 77 7g a<3> a<3> 78 9g nc/288m a<21> 79 10g a<1> a<1> 80 11g nc/576m nc/288m 81 13g a<4> a<4> 82 12f a<14> a<14> 83 10f a<0> a<0> 84 8f a<13> a<13> 85 10d cfg# cfg# 86 10b lbk#<1> lbk#<1> 87 10a lbk#<0> lbk#<0> 88 8a dqa<8> dqa<8> 89 7b dqa<1> dqa<1> 90 6a dqa<7> dqa<7> 91 5b dqa<17> nc 92 4a dqa<5> dqa<5> 93 2b dqa<13> nc 94 3c qvlda<0> qvlda<0> 95 4c qka<0> qka<0> boundary scan order (continued) bit bump cy7c4142kv13 cy7c4122kv13 36 device 18 device cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 29 of 51 96 6c dqa<2> dqa<2> 97 8c dqa<0> dqa<0> 98 8d dinva<0> dinva<0> 99 7d dqa<4> dqa<4> 100 5d dqa<3> dqa<3> 101 3d qka#<0> qka#<0> 102 2e dqa<14> nc 103 3f dka#<0> dka#<0> 104 4f dka<0> dka<0> 105 5f dqa<6> dqa<6> 106 4g dqa<16> nc 107 2g dqa<15> nc 108 3h dqa<9> nc 109 5h dqa<10> nc 110 4j dqa<12> nc 111 2j dqa<11> nc 112 2l dqb<11> nc 113 4l dqb<12> nc 114 5m dqb<10> nc 115 3m dqb<9> nc 116 2n dqb<15> nc 117 4n dqb<16> nc 118 5p dqb<6> dqb<6> 119 4p dkb<0> dkb<0> 120 3p dkb#<0> dkb#<0> 121 2r dqb<14> nc 122 3t qkb#<0> qkb#<0> 123 5t dqb<3> dqb<3> 124 7t dqb<4> dqb<4> 125 8t dinvb<0> dinvb<0> 126 8u dqb<0> dqb<0> 127 6u dqb<2> dqb<2> 128 4u qkb<0> qkb<0> 129 3u qvldb<0> qvldb<0> 130 2v dqb<13> nc 131 5v dqb<17> nc 132 7v dqb<1> dqb<1> 133 8w dqb<8> dqb<8> 134 6w dqb<7> dqb<7> 135 4w dqb<5> dqb<5> boundary scan order (continued) bit bump cy7c4142kv13 cy7c4122kv13 36 device 18 device cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 30 of 51 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ..... ............... ............... ?55 c to +125 c maximum junction temperature ................................. 125 c supply voltage on v dd relative to gnd ..................................?0.3 v to +1.35 v supply voltage on v ddq relative to gnd ................................?0.3 v to +1.35 v dc input voltage ........ ............... ........... ......?0.3 v to +1.35 v current into outputs (low) ...... ..................................... 20 ma static discharge voltage (mil-std-883, m. 3015) ......................................... > 2001v latch up current ..................................................... > 200 ma operating range neutron soft error immunity table 18. operating range range case temperature (t c ) v dd v ddq commercial 0 c to +70 c 1.3 v 40 mv 1.1 v 50 mv 1.2 v 50 mv table 19. neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single-bit upsets 25 c 0 0.01 fit/mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/mb sel single event latch-up 85 c 0 0.1 fit/dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculation. fo r more details refer to application note, accelerated neutron ser testing and calculation of terrestrial failure rates ? an54908. electrical characteristics over the operating range parameter description min typ max unit pod signaling mode v dd [4] core supply voltage (1.3 v 40 mv) 1.26 1.3 1.34 v v ddq [4] pod i/o supply voltage (1.1 v 50 mv) 1.05 1.1 1.15 v pod i/o supply voltage (1.2 v 50 mv) 1.15 1.2 1.25 v v ref [4, 5] pod reference voltage v ddq 0.69 v ddq 0.7 v ddq 0.71 v v ol(dc) [4] pod low-level output voltage (dc) ? ? 0.5 v v ih(dc) [4, 6] pod high-level input voltage (dc) v ref + 0.08 ? v ddq + 0.15 v v il(dc) [4, 6] pod low level input voltage ?0.15 ? v ref ? 0.08 v v ih(ac) [4, 7] pod high-level input voltage (dc) v ref + 0.15 ? ? v v il(ac) [4, 7] pod low-level input voltage ? ? v ref ? 0.15 v v mp(dc) pod differential input mid-point voltage; pin and pin# v ref ? 0.08 ? v ref + 0.08 v v id(dc) pod differential input differential voltage (dc); pin and pin# 0.16 ? ? v v id(ac) pod differential input differential voltage (ac); pin and pin# 0.30 ? ? v v in pod single-ended input voltage; pin and pin# 0.27 ? v ddq + 0.15 v v ins pod single-ended input voltage slew rate; pin and pin# 3 ? ? v/ns v ix(ac) pod differential input crossing point voltage (ac); pin and pin# v ref ? 0.08 ? v ref + 0.08 v notes 4. all voltages referenced to vss (gnd). 5. peak to peak ac noise on v ref must not exceed +/?2% v ddq (dc). 6. v ih /v il (dc) are specified with odt disabled. 7. v ih /v il (ac) is a test condition specified to g uarantee at which the receiver must meet its timing specifications with odt enabled. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 31 of 51 i x [8] pod input leakage current ? ? 200 a i oz [8] pod output leakage current ? ? 200 a i dd [9, 10] v dd operating supply (1066 mhz, 18) ? 2800 4100 ma v dd operating supply (1066 mhz, 36) ? 3920 4500 ma v dd operating supply (933 mhz, 18) ? 2520 3400 ma v dd operating supply (933 mhz, 36) ? 3520 4000 ma hstl/sstl signaling mode v dd [11] core supply voltage (1.3 v 40 mv) 1.26 1.3 1.34 v v ddq [11] i/o supply voltage (1.2 v 50 mv) 1.15 1.2 1.25 v i/o supply voltage (1.25 v 50 mv) 1.2 1.25 1.3 v v ref(dc) [11, 12] hstl/sstl reference voltage (dc) v ddq 0.48 v ddq 0.5 v ddq 0.52 v v ref(ac) [11, 12] hstl/sstl reference voltage (ac) v ddq 0.47 v ddq 0.5 v ddq 0.53 v v ih(dc) [11, 13] hstl/sstl high-level input voltage (dc) v ref + 0.08 ? v ddq + 0.15 v v il(dc) [11, 13] hstl/sstl low-level input voltage (dc) ?0.15 ? v ref ? 0.08 v v ih(ac) [11, 14] hstl/sstl high-level input voltage (ac) v ref + 0.15 ? v ddq + 0.24 v v il(ac) [11, 14] hstl/sstl low-level input voltage (ac) ?0.24 ? v ref ? 0.15 v v oh(dc) [11] hstl/sstl high-level output voltage (dc) ? i oh = ?0.25 v ddq /r oh v ddq 0.712 v ddq 0.75 ? v v ol(dc) [11] hstl/sstl low-level output voltage (dc) ? i ol = 0.25 v ddq /r ol ? v ddq 0.25 v ddq 0.288 v v ix hstl/sstl input voltage cross-point ? v ddq 0.5 ? v v dif(ac) hstl/sstl ac input differential voltage 0.30 ? v ddq + 0.48 v v dif(dc) hstl/sstl dc input differential voltage 0.16 ? v ddq + 0.30 v v dif(cm) hstl/sstl dc common mode input v ddq 0.4 v ddq 0.5 v ddq 0.6 v v ox hstl/sstl output voltage cross-point ? v ddq 0.5 ? v v out(ac) hstl/sstl ac output voltage ?0.24 ? v ddq + 0.24 v v out(dc) hstl/sstl dc output voltage ?0.15 ? v ddq + 0.15 v i x [8] hstl/sstl input leakage current ? ? 200 a i oz [8] hstl/sstl output leakage current ? ? 200 a i dd [9, 10] v dd operating supply (1066 mhz, 18) ? 2800 4100 ma v dd operating supply (1066 mhz, 36) ? 3920 4500 ma v dd operating supply (933 mhz, -18) ? 2520 3400 ma v dd operating supply (933 mhz, -36) ? 3520 4000 ma electrical characteristics (continued) over the operating range parameter description min typ max unit notes 8. output driver into high z with odt disabled. 9. the operation current is calculated with 50% read cycle and 50% write cycle. 10. typical operation current specif ications are tested at 1.3v v dd . 11. all voltages referenced to vss (gnd). 12. peak to peak ac noise on v ref must not exceed +/?2% v ddq (dc). 13. v ih /v il (dc) are specified with odt disabled. 14. v ih /v il (ac) is a test condition specified to guarantee at which the receiver must meet its timing specifications with odt enabled. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 32 of 51 capacitance thermal resistance table 20. capacitance parameter [15] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 1.3 v, v ddq = 1.25 v 4 pf c o output capacitance 4pf table 21. thermal resistance parameter [15] description test conditions 361-ball fcbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. with still air (0 m/s) 12.00 c/w with air flow (1 m/s) 10.57 c/w with air flow (3 m/s) 9.09 c/w ? jb thermal resistance (junction to board) 3.03 c/w ? jc thermal resistance (junction to case) 0.029 c/w ac test load and waveform figure 7. ac test load and waveform note 15. tested initially and after any design or proc ess change that may affect these parameters. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 33 of 51 switching characteristics over the operating range [16, 17, 18, 19, 20, 21, 22, 23] cypress parameter description 1066 mhz 933 mhz unit min max min max t ck ck, dkx, qkx clock period 0.938 1.875 1.071 2.143 ns t ckl ck, dkx low time 0.45* ? 0.45* ? t ck t ckh ck, dkx high time 0.45* ? 0.45* ? t ck t jit (per) clock period jitter ?0.055 0.055 ?0.060 0.060 ns t jit (cc) cycle-to-cycle jitter ? 0.110 ? 0.120 ns t as a to ck setup 0.125 ? 0.135 ? ns t ah ck to a hold 0.125 ? 0.135 ? ns t ash ck to a setup-hold window 0.170 ? 0.180 ? ns t cs ldx#, rwx# to ck setup 0.150 ? 0.180 ? ns t ch ck to ldx#, rwx# hold 0.150 ? 0.180 ? ns t csh ck to ldx#, rwx# setup-hold window 0.170 ? 0.180 ? ns t ckdk ck to dkx skew ?0.15 0.15 ?0.172 0.172 ns t is dqx, dinvx to dkx setup 0.125 ? 0.135 ? ns t ih dkx to dqx, dinvx hold 0.125 ? 0.135 ? ns t ish0 dkx[0] to dqx[17:0], dinvx[0] ( 36) or dkx[0] to dqx[8:0], dinvx[ 0] ( 18) setup-hold window 0.150 ? 0.180 ? ns t ish1 dkx[1] to dqx[35:18], dinvx[1] ( 36) or dkx[1] to dqx[17:9], dinvx[ 1] ( 18) setup-hold window 0.150 ? 0.180 ? ns t rise (se) single-ended output signal rise time 20%-80% 2 6 2 6 v/ns t fall (se) single-ended output signal fall time 20%-80% 2 6 2 6 v/ns t rise (diff) differential output signal rise time 20%-80% 3 10 3 10 v/ns t fall (diff) differential output signal fall time 20%-80% 3 10 3 10 v/ns t qkl qkx low time 0.45* ? 0.45* ? t ck t qkh qkx high time 0.45* ? 0.45* ? t ck t ckqk ck to qkx skew ?0.225 0.225 ?0.257 0.257 ns t qkq0 qkx[0] to dqx[17:0], dinvx[0] ( 36) or qkx[0] to dqx[8:0], dinvx[0] ( 18) ? 0.075 ? 0.085 ns t qh0 qkx[0] to dqx[17:0], dinvx[0] ( 36) or qkx[0] to dqx[8:0], dinvx[0] ( 18) 0.40* ? 0.40* ? t ck t qkq1 qkx[1] to dqx[35:18], dinvx[1] ( 36) or qkx[1] to dqx[17:9], dinvx[1] ( 18) ? 0.075 ? 0.085 ns t qh1 qkx[1] to dqx[35:18], dinvx[1] ( 36) or qkx[1] to dqx[17:9], dinvx[1] ( 18) 0.40* ? 0.40* ? t ck notes 16. x refers to port a and port b. for example, dqx refers to dqa and dqb. 17. input hold timing assumes rising edge sl ew rate of 4 v/ns measured from v il /v ih (dc) to v ref . 18. input setup timing assumes falling edge slew rate of 4 v/ns measured from v ref to v il /v ih (ac). 19. all output timing assumes the load shown in figure 7 on page 32 . 20. setup/hold window, t ash, t csh, t ish are used for pin to pin timing budgeting and cannot be directly applied without performing de-skew training. 21. clock phase jitter is the variance from clo ck rising edge to the next expected clock rising edge. 22. frequency drift is not allowed. 23. t qkl , t qkh , t qkq , t qkqx , t ash , t csh and t ish are guaranteed by design. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 34 of 51 t qkqv0 qkx[0] to qvldx ? 0.112 ? 0.128 ns t qvh0 qkx[0] to qvldx 0.85* ? 0.85* ? t ck t qkqv1 qkx[1] to qvldx ? 0.112 ? 0.128 ns t qvh1 qkx[1] to qvldx 0.85* ? 0.85* ? t ck t pwr v dd (typical) to the first access 200 ? 200 ? ms t rss rst# pulse width 200 ? 200 ? s t rsh rst# deasserted to fi rst active command 400000* ? 400000* ? t ck t rds a to rst# setup 500* ? 500* ? t ck t rdh a to rst# hold 500* ? 500* ? t ck t tss trst# pulse width 200 ? 200 ? s t tsh trst# deasserted to first jtag command 200 ? 200 ? s t pll time for pll to stabilize after being reset ? 100 ? 100 s t lbl loopback latency 16* 16* 16* 16* t ck t cd loopback output delay ? 5 ? 5 ns t cfgs active mode to configuration mode 32* ? 32* ? t ck t cfgh configuration mode to active mode register access without odt or pll programming updates 32* ? 32* ? t ck t cfgh configuration mode to active mode register access with odt programming updates 4096* ? 4096* ? t ck t cfgh configuration mode to active mode register access with pll programming updates 100 ? 100 ? s t cfgd configuration command to configuration command 80* ? 80* ? t ck t clds cfg# assertion to lda# assertion 32* ? 32* ? t ck t cldh lda# deassertion to cfg# deassertion 32* ? 32* ? t ck t cldw lda# pulse width for configuration command 16* ? 16* ? t ck t crdl lda# assertion to read data latency ? 32* ? 32* t ck t crdh cfg# deassertion to read data hold 0* 32* 0* 32* t ck t dqvld dqax to qvlda<0> in configuration mode ?2 2 ?2 2 t ck switching characteristics (continued) over the operating range [16, 17, 18, 19, 20, 21, 22, 23] cypress parameter description 1066 mhz 933 mhz unit min max min max cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 35 of 51 switching waveforms figure 8. rise and fall time definitions for output signals nominal rise-fall time definiti on for single-ended output signals nominal rise-fall time definiti on for differential output signals cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 36 of 51 figure 9. input and output timing waveforms switching waveforms (continued) address and command input timin g data input timing data output timing cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 37 of 51 figure 10. waveforms for 8.0 cycle read latency (read to write timing waveform) figure 11. waveforms for 8.0 cycle read latency (write to read timing waveform) switching waveforms (continued) cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 38 of 51 figure 12. configuration write timing waveform figure 13. configuration read timing waveform switching waveforms (continued) note: dqa[x:8] and dqb data bus is a don?t care in configuration mode cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 39 of 51 figure 14. configuration write and read timing waveform switching waveforms (continued) note: dqa[x:8] and dqb data bus is a don?t care in configuration mode note: dqa[x:8] and dqb data bus is a don?t care in configuration mode (a) configuration multiple cycle - write followed by read operation (b) configuration multiple cycle - back to back read operation cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 40 of 51 figure 15. loopback timing switching waveforms (continued) loopback timing cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 41 of 51 figure 16. reset timings switching waveforms (continued) cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 42 of 51 ordering code definitions ordering information the following table table 22 contains only the parts that are currently available. if you do not see what you are looking for, contact your local sales representative. for more information, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. table 22. ordering information speed (mhz) ordering code package diagram package type operating range 1066 CY7C4122KV13-106FCXC 001-70319 361-ball fcbga (21 21 2.515 mm) pb-free commercial cy7c4142kv13-106fcxc 933 cy7c4122kv13-933fcxc 001-70319 361-ball fcbga (21 21 2.515 mm) pb-free commercial cy7c4142kv13-933fcxc cy 7c41x2 k v13 - xxx fc x c temperature range: c = commercial pb-free package type: 361-ball flip chip bga speed grade: 106 = 1066 mhz or 933 = 933 mhz vdd = 1.3 v die revision: k = 65nm part identifier: 4122 or 4142 technology code: c = cmos marketing code: 7 = sram company id: cy = cypress cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 43 of 51 package diagram figure 17. 361-ball fcbga (21 21 2.515 mm) fr0aa package outline, 001-70319 001-70319 *d cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 44 of 51 acronyms document conventions units of measure table 23. acronyms used in this document acronym description ddr double data rate rtr random transaction rate eia electronic industries alliance emi electromagnetic interference fcbga flip-chip ball grid array i/o input/output jedec joint electron devices engineering council jtag joint test action group lmbu logical multiple bit upset lsb least significant bit lsbu logical single bit upset msb most significant bit odt on-die termination pll phase locked loop qdr quad data rate sdr single data rate sel single event latch-up ser soft error rate sram static random access memory tap test access port tck test clock tdi test data-in tdo test data-out tms test mode select table 24. units of measure symbol unit of measure c degree celsius mhz megahertz a microampere s microsecond ma milliampere mm millimeter ms millisecond mv millivolt ns nanosecond ? ohm % percent pf picofarad vvolt wwatt cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 45 of 51 errata this section describes the errata for the 144-mb qdr-iv srams. details include errata trigger conditions, scope of impact, avai lable workaround, and silicon revision applicability. part numbers affected qdr-iv qualification status product status: in production qdr-iv errata summary the following table defines the errata applicab ility to available qdr-iv family devices. part number device characteristics cy7c4122kv13 / cy7c4142kv13 144-mbit qdr-iv xp sram items part number silicon revision fix status 1. on-die termination (odt) auto update failure. cy7c4122kv13 cy7c4142kv13 revision *c (before dc1444) [24] fixed in revision *d silicon (from dc1445) 2. failure occurs during the no operation (nop) followed by the read operation. note 24. dcxxyy: ?dc = date code?, ?xx = year 20xx?, ?yy = week yy?. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 46 of 51 1. on-die termination (odt ) auto update failure. qdr-iv srams support odt for address, control, clock and data pins. the odt feature calibrate s and updates the termination resistance value every 19 s if the ?odt/zq auto update? configur ation register is set to logic high. problem definition the odt auto update functionality does not always update the corre ct odt value, which can result in the wrong input impedance value and thereby affecting the input vil/vih levels (refer to the following figure). figure 18. odt auto update timing in the case of a correct odt value update , the qdr-iv gets the input signal with corre ct vih/vil level (signal in green) while in the other case, the input signal attenuates (signal in red) because of the wrong od t value update and qdr-iv might not recogniz e the accurate input signal. figure 19. input signal representation during odt update parameters affected the electrical characteristics parameters relat ed to input signal voltage levels are affected. parameter description vih (dc) pod/hstl/sstl high-level input voltage vil (dc) pod/hstl/sstl low level input voltage vih (ac) pod/hstl/sstl high-level input voltage vil (ac) pod/hstl/sstl low-level input voltage vid (dc) pod differential input differential voltage (dc) vid (ac) pod differential input differential voltage (ac) vin pod single-ended input voltage vdif (ac) hstl/sstl ac input differential voltage vdif (dc) hstl/sstl dc input differential voltage vdif (cm) hstl/sstl dc common mode input cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 47 of 51 trigger condition configuring odt/zq auto update configuration register to logic high. scope of impact causes write and read operation failure. workaround configure the odt values for the respective input pins and e nable the odt/zq auto update conf iguration register (logic high) during the power-up by providing the data th rough a[13:0] at the rising edge of the reset. during this operation, address bit a 6 updates the odt/zq auto update configurat ion register bit. then disable the odt/zq auto update configuration register (logic low) during the configuration step (refer to the following figur e). as a result, the odt auto update will be disabled during th e normal qdr-iv sram operation, but the correct termination value will be set. figure 20. workaround (memory configuration) however, the odt value might vary because of the temperature or voltage variations. in this case as shown in the following figu re, perform the manual odt update by entering in to the configurat ion mode and update all the odt configuration registers (ku, iu and qu). the manual odt update can be scheduled when memory is not being accessed. figure 21. workaround (manual odt configuration) fix status the fix for the above issue has been identified and the new silic on available in january, 2015 will not have this defect. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 48 of 51 2. failure occurs during the no operation (nop) followed by the read operation. problem definition qdr-iv sram read operations intermitte ntly fail with a no operation (nop) follow ed by a read operation. the following figure explains about port a operation (at rising edge) and the sa me explanation can be applied to port b (at falling edge). figure 22. write ? nop ? read condition figure 23. read ? nop ? read condition parameters affected functional failures. trigger condition(s) no operation (nop) followed by the read oper ation sometimes resulting in a read failure. scope of impact causes read operation failure on output data bits. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 49 of 51 workaround there are three identified workarounds to avoid nop before the read operation. a. in the case of write operation ? nop ? read operation sequence if possible, ignore the nop betwe en the write and read operati on and perform a write operation followed by the read oper ation to avoid the nop prio r to the read operation. figure 24. write ? read condition b. insert the dummy reads between the real read operations to avoi d the nop between the read operations. for an example, if the functionality needs one or two nop cycles between the read operat ions then insert the dummy reads accordingly instead of nop cycles as shown in the figure below. figure 25. read ? dummy read ? read condition c. in the case of nop followed by the read operation, perform tw o dummy reads and only consider the data from the third read access (ignore the data from the first two read accesses) figure 26. nop ? dummy read ? read condition fix status the fix for the above issue has been identified and the new si licon available in january, 2015 will not have this defect. cy7c4122kv13/cy7c4142kv13 document number: 001-68255 rev. *m page 50 of 51 document history page document title: cy7c4122kv13/cy7c 4142kv13, 144-mbit qdr?-iv xp sram document number: 001-68255 rev. ecn submission date orig. of change description of change *j 4283232 03/25/2014 prit post to web. *k 4410859 06/17/2014 prit updated ac test load and waveform : updated figure 7 (changed value of rq resistor from 200 ? to 180 ? ). updated switching characteristics : added t ash , t csh , t ish parameters and their details. updated note 20 and 23. completing sunset review. *l 4502995 09/15/2014 prit updated switching characteristics : updated note 23. updated package diagram : spec 001-70319 ? changed revision from *c to *d. *m 4573944 11/19/2014 prit updated functional description : added ?for a complete list of related resources, click here .? at the end. added errata . document number: 001-68255 rev. *m revised november 19, 2014 page 51 of 51 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c4122kv13/cy7c4142kv13 ? cypress semiconductor corporation, 2011-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support 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